1. Field of the Invention
The present invention relates to operating margin improvements of a frequency dividing circuit, a power supply circuit and a display device.
2. Description of the Background Art
A flat display device includes a power supply circuit and a drive circuit as well as a display element (pixel) made of liquid crystal, organic EL, or the like. The power supply circuit and drive circuit are formed by using thin film transistors (TFTs) that are formed on a substrate simultaneously with the display element.
The power supply circuit includes a frequency dividing circuit and a charge pump circuit, and is supplied with a voltage VDD from an external system and a voltage VSS (GND). The frequency dividing circuit lowers the frequency of a high-frequency clock signal input thereto, and outputs a low-frequency clock signal to the charge pump circuit. The reason for lowering the frequency of the clock signal is to minimize reactive current flowing to the charge pump circuit, thus enhancing energy efficiency of the power supply circuit.
The charge pump circuit uses the low-frequency clock signal, VDD (input voltage) and VSS to produce a voltage VDDH (second booster voltage) higher than VDD, and a voltage VSSL lower than VSS. The drive circuit is activated by VDDH and VSSL to produce various kinds of signals for driving pixels.
The frequency dividing circuit includes a plurality of cascade-connected unit frequency dividing circuits (binary counters). The unit frequency dividing circuits each lower the frequency of an input signal to half. Thus, a frequency dividing circuit having n stages of cascade-connected unit frequency dividing circuits lowers the frequency of an input signal to (1/2n).
A display device having a pixel, a drive circuit and a power supply circuit integrated into one another is in general supplied with three signals as a clock signal, namely, a dot clock signal (input signal) for producing control signals inside the display device, a horizontal synchronizing signal, and a vertical synchronizing signal. The frequencies of the horizontal and vertical synchronizing signals are lower than a frequency that satisfies the load-current-supplying capability of the power supply circuit. Thus, the dot clock signal is input to the frequency dividing circuit.
The frequency of the dot clock signal depends on the number of pixels of a display device, which is approximately 5 MHz in a QVGA-size display device used in a cellular phone. An operation of approximately 5 MHz is therefore required of the unit frequency dividing circuit in the first stage. The reference voltage VDD depends on an external LSI circuit, which in general is approximately 3 V.
Prior art pertinent to the present invention is disclosed in Japanese Patent Application Laid-Open No. 2000-278937.
The present TFT formed by a low-temperature polysilicon process, however, is low in current driving capability, and will not follow a high-frequency input signal well. With variations in characteristic values (especially, a threshold voltage) of the TFT, the unit frequency dividing circuit in the first stage is supplied with the highest frequency signal that leaves virtually no operating margin. This results in a reduction in operating margin of the frequency dividing circuit as a whole.